Line Control Register - IBM CPC700 User Manual

7.2.1.1 Line Control Register

The system programmer uses the line control register (LCR) to specify the format of the asynchronous
data communications exchange and to set the Divisor Latch Access Bit. The contents of the LCR can also
be read by the processor. The read capability simplifies system programming, and eliminates the need for
separate storage of the line characteristics in system memory.
Bit # Value
0 0
1
1 0
1
2 0
1
3 0
1
4 0
1
5 0
1
6 and 7 Bit 6 = 0
Bit 7 = 0
Bit 6 = 0
Bit 7 = 1
Bit 6 = 1
Bit 7 = 0
Bit 6 = 1
Bit 7 = 1
CPC700 User's Manual—Preliminary
Table 72. Line Control Register Description
LCR Bits
Divisor Latch Access Bit. Required to address RBR, THR and IER with LTADR2-0 for read or
write operation.
Divisor Latch Access Bit. Required to address Divisor Latches with LTADR2-0 for read or write
operation.
Break Control Bit. The break is disabled.
Break Control Bit. It causes a break condition to be transmitted to the UART when the core is
receiving. SOUT is forced to the spacing state (logic 0). This bit acts only on SOUT and has no
effect on the transmitter logic.
Sticky Parity Bit. Stick parity is disabled.
Sticky Parity Bit. When bits 4 and 3 are logic 1, the parity bit is transmitted and checked as logic 0.
If bit 4 is logic 1 and bit 3 is a logic 0, then the parity bit is transmitted and checked as logic 1.
Even Parity Select Bit. When bit 3 is a logic 1, an odd number of logic 1's is transmitted or
checked in the data word and the parity bits.
Even Parity Select Bit. When bit 4 is a logic 1, an even number of logic 1's is transmitted or
checked in the data word and the parity bits.
Parity Enable Bit. Parity checking is disabled.
Parity Enabled. A parity bit is generated during transmission of data (or checked during the
reception of data) between the last data word bit and the stop bit of the serial data. The parity bit
is used to produce an odd or even number of 1's when the data word bits and the parity bit are
summed.
Specifies one stop bit transmitted and received in each serial character. The receiver checks the
first stop bit only, regardless of how many stop bits are selected.
If 5-bit word length is selected via bits 7 and 6, one and one half stop bits are generated. If any
other character length is selected, two stop bits are generated. The receiver checks the first stop
bit only, regardless of how many stop bits are selected.
specifies five bits as length for each transmitted or received serial character.
specifies six bits as length for each transmitted or received serial character.
specifies seven bits as length for each transmitted or received serial character.
specifies eight bits as length for each transmitted or received serial character.
Description
7-5