Ecc Specific Registers; Ecccf - Ecc Configuration Register - IBM CPC700 User Manual

4.9.4 ECC Specific Registers
4.9.4.1 ECCCF - ECC Configuration Register
Address Offset: x94
Width 32
Reset Value: x0000_0000
Access: Read/Write
This register is used to configure ECC operation.
NOTE: Bit 4 of the ECCCF register, SD_WDTH, is an SDRAM related control bit used to set the SDRAM
data bus width.
Bit
Name
0 ECC_MODE
1 ECC_EN
2:3
4 SD_WDTH
5:7
8 ECC_BANK0_EN
9 ECC_BANK1_EN
4-56
Reset Description
Value
0 ECC Mode
0 - 64-bit Mode
1 - Dual 32-bit Mode
0 ECC Enable
0 - ECC Disable
1 - ECC Enable
0 Reserved
0 SDRAM Data Bus Width
0 - 64-bit Width
1 - 32-bit Width
0 Reserved
0 ECC Bank 0 Enable
0 - Bank Disabled
1 - Bank Enabled
If ECC is globally enabled (bit[1]=1), these bits (8-16)
control how the ECC controller will perform memory
writes of less than 8 bytes. When a BANKn Enable is
set to 1, the controller will perform a read-modify-write
operation. When a BANKn enable is set to 0, the con-
troller will use the byte selects (DQMs) to perform the
write. This capability allows the CPC700 to support
mixing of ECC and non-ECC banks. In systems which
support ECC and therefore have a single DQM output,
less than 8-byte writes to non-ECC banks will result in
a read-modify-write operation.
0 ECC Bank 1 Enable
0 - Bank Disabled
1 - Bank Enabled
Memory Controller