Rom Timing Diagrams; Figure 29. Single Read/Write (General); Figure 30. Burst Mode Read - IBM CPC700 User Manual

Memory controller and pci bridge
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4.6.8 ROM Timing Diagrams

1
Clock
ALE
MA
READ#
WRITE#
RNW
CS#
OE#
WE#
W_DATA
R_DATA
1
2
3
Clock
ALE
MA
READ#
WRITE#
RNW
CS#
OE#
R_DATA
4-34
2
3
4
CSON
0-3
0-3

Figure 29. Single Read/Write (General)

4
5
6
7
8
9
1+FWT
CSON
0-3
OEON
0-3
NOT READY

Figure 30. Burst Mode Read

5
6
7
1+TWT
OEON
WEON
0-3
0
OEON
0-3
11
10
12 13 14 15 16 17
1+NWT
1+NWT
Data Sampled
11
8
9
10
THDRD
THDWR
WEOFF
1
Data Sampled On READS
18
19
20
21 22
THDRD
Memory Controller
12
23

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