Communication Between The Plc Cpu And The Motion Cpu In The Multiple Cpu System; Cpu Shared Memory - Mitsubishi Electric Q Series Programming Manual

2 MULTIPLE CPU SYSTEM

2.3 Communication Between the PLC CPU and the Motion CPU in the Multiple CPU System

2.3.1 CPU shared memory

(0H)
to
(1FFH) 511
(200H) 512
to
(7FFH) 2047
(800H) 2048
to
(FFFH) 4095
(1000H) 4096
to
(270FH) 9999
(2710H) 10000
to
up to
(5F0FH) 24335
(1) Structure of CPU shared memory
The CPU shared memory is memory provided for each CPU module and by
which data are written or read between CPU modules of the Multiple CPU
system.
The CPU shared memory consists of four areas.
• Self CPU operation information area
• System area
• User setting area
• Multiple CPU high speed transmission area
The CPU shared memory configuration and the availability of the communication
from the self CPU using the CPU shared memory by program are shown below.
CPU shared memory
0
Self CPU operation
to
information area
to System area
to User setting area
to Unusable
Multiple CPU high speed
transmission area
to
(Variable size in 0 to
14k[points]: 1k words in unit)
REMARK
(Note-1): Use the MULTW instruction to write to the user setting area of the self
CPU in the Motion CPU.
Use the S. TO instruction to write to the user setting area of the self CPU in
the PLC CPU.
(Note-2): Use the MULTR instruction to read the shared memory of self CPU and
other CPU in the Motion CPU.
Use the FROM instruction/Multiple CPU area device (U \G ) to read the
shared memory of the Motion CPU from the PLC CPU.
(Note-3): Refer to Section 2.3.2(1) for the access method of Multiple CPU high
speed transmission area.
Self CPU
Write
(Note-1)
Multiple CPU
(Note-3)
high speed
bus
: Communication allowed
2 - 12
Other CPU
Read Write Read
(Note-2)
(Note-2)
(Note-3)
: Communication not allowed
(Note-2)
(Note-2)
(Note-2)
(Note-3)