Mitsubishi Electric Q Series Programming Manual page 170

Common. motion controller
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4 AUXILIARY AND APPLIED FUNCTIONS
System configuration
Q61P
QnUD
Q172D
QY40P QY40P Q172D
CPU
CPU
AMP
Axis 1
M
(a) Sequence program
SM400
0
M100
M101
M102
5
M10
M100
18
M10
M11
M101
M12
39
M12
M13
M102
M10
57
M10
M11
M103
M12
78
M12
M13
M104
M10
96
M10
M11
(b) Program to connect/disconnect the servo amplifiers after Axis 5 connected
to the Motion CPU (CPU No.2) by the PLC CPU (CPU No.1).
Disconnect procedure : Turn OFF the servo amplifier's power supply after
Connect procedure
QY40P
LX
AMP
AMP
AMP
Axis 2
Axis 3
Axis 4
M
M
M
X0
X1
DP.DDRD H3E1
=
D100
K0
DP.DDWR H3E1
DP.DDRD H3E1
=
D100
K-1
DP.DDWR H3E1
DP.DDRD H3E1
=
D100
K0
checking the LED display "AA" of servo amplifier by
turning X0 from OFF to ON.
: Resume operation of servo amplifier after checking
the servo ready (M2415+20n) of servo amplifier by
turning X1 from OFF to ON.
Disconnection (After Axis 5)
AMP
AMP
AMP
Axis 5
Axis 6
Axis 7
M
M
MOV
K1
D51
MOV
K-2
D104
MOV
K5
D102
SET
M100
MOV
K-10
D102
SET
M100
D50
SD508
D100
M10
RST
M100
SET
M101
D50
D102
SD803 M12
RST
M101
SET
M102
D50
SD508
D100
M10
RST
M102
SET
M103
D50
D104
SD803 M12
RST
M103
SET
M104
D100
D50
SD508
M10
RST
M104
4 - 55
AMP
Axis 8
M
M
Set "-2: Execute command" in D104.
Set "5: Disconnect command of SSCNET
communication" (Disconnect after Axis 5)
in D102.
Set "-10: Connect command of SSCNET
communication" in D102.
Read the data of SD508 for Multiple CPU
system (CPU No.2) by turning M100 ON, and
store them to data area (D100) of self CPU.
Write D102 to the data of SD803 for Multiple
CPU system (CPU No.2) by turning M101 ON.
(Disconnect/Connect command)
Read the data of SD508 for Multiple CPU
system (CPU No.2) by turning M102 ON, and
store them to data area (D100) of self CPU.
Write D104 to the data of SD803 for Multiple
CPU system (CPU No.2) by turning M103 ON.
(Disconnect/connect execute command)
Read the data of SD508 for Multiple CPU
system (CPU No.2) by turning M104 ON, and
store them to data area (D100) of self CPU.

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