Multiple Cpu High Speed Transmission - Mitsubishi Electric Q Series Programming Manual

2 MULTIPLE CPU SYSTEM

2.3.2 Multiple CPU high speed transmission

CPU No.1 (PLC CPU)
Sequence program
SM400
U3E0\
MOV W0 G10000
U3E0\
G10010.1
SM400
U3E0\
MOV W1 G10100
U3E0\
G10110.5
END
(1) Multiple CPU high speed transmission
Multiple CPU high speed transmission is a function for fixed cycle data
transmission between Multiple CPUs (Multiple CPU high speed transmission
cycle is 0.88[ms].).
Secure data transmission is possible without effecting the PLC CPU scan time or
Motion CPU main cycle because the data transmission and execution of
sequence program and Motion SFC program/Motion program can be executed
with parallel processing.
High speed response between multiple CPUs is realized by synchronizing the
Multiple CPU high speed transmission cycle with Motion CPU operation cycle.
The following methods of data transmission exist between Multiple CPUs for
Multiple CPU high speed transmission.
• Use the Multiple CPU area device
Set the Multiple CPU high speed transmission area by setting the Multiple CPU
area device (U \G ) in the program.
• Automatic refresh method
Refresh the internal devices of each CPU by automatic refresh via "Multiple
CPU high speed transmission area".
(a) Multiple CPU area device method
CPU shared memory
(User setting area
U3E0\G10000
1)
U3E0\G10010
CPU No.1
transmitting
data
U3E0\G10100
4)
U3E0\G10110
1), 4) : Write data in the user setting area
3), 6) : Read data from the user setting area
2), 5) : Transmit the contents of user setting area
Note-1: The area composed in the Multiple CPU high speed transmission area.
(Refer to Section "(3) Memory configuration of Multiple CPU high speed transmission area".)
CPU No.2 (Motion CPU)
CPU shared memory
(Note-1) ) (User setting area
U3E0\G10000
2)
U3E0\G10010
CPU No.1
transmitting
5)
U3E0\G10100
U3E0\G10110
Multiple CPU high speed
transmission in 0.88ms cycle
by the instruction that uses the Multiple CPU area device.
(Note-1)
by the instruction that uses the Multiple CPU area device.
(Note-1)
to the other CPU with by Multiple CPU high speed transmission in 0.88ms cycle.
(Note-1)
2 - 15
Motion SFC program
(Note-1) )
G0
3)
U3E0\G10010.1
F0
W0=U3E0\G10000
data
6)
G1
U3E0\G10110.5
F1
W1=U3E0\G10100