Mitsubishi Electric Q Series Programming Manual page 262

APPENDICES
Table 4.1 Differences between Q173DSCPU/Q172DSCPU/Q173DCPU(-S1)/
Q172DCPU(-S1)/Q173HCPU/Q172HCPU (Continued)
Item
SV13/
SV22
Motion dedicated
PLC instructions
SV43
Interlock condition
SV13
Motion modules
SV22
SV43
System setting
Latch clear
RUN/STOP
ROM operation
SV13/
Model of operating
SV22
system software
SV43
CPU module No.1
Installation orders CPU No.2
or later
Combination of Motion CPU
modules
CPU empty slot
Multiple CPU
high speed
transmission
CPU
area
shared
memory
Access by
Multiple CPU
shared memory
Q173DSCPU/Q172DSCPU
D(P).DDRD, D(P).DDWR,
D(P).SFCS, D(P).SVST,
D(P).CHGT, D(P).CHGT2,
(Note-2)
D(P).CHGV, D(P).CHGVS
(Note-2)
D(P).CHGA, D(P).CHGAS
D(P).GINT
—
Multiple instructions are executable continuously without interlock
condition by the self CPU high speed interrupt accept flag from CPU .
:CPU No.
Q172DLX, Q173DPX, Q173DSXY
Q172DLX, Q172DEX, Q173DPX,
Q173DSXY
—
• QnUD(E)(H)CPU/QnUDVCPU is set as CPU No.1.
• Only Multiple CPU high speed main base unit
(Q35DB/Q38DB/Q312DB) can be used as main base unit.
• Q172DLX, Q172DEX and Q173DPX cannot be installed to I/O 0 to 2
slot.
Remote operation
Remote operation, RUN/STOP switch
• ROM writing is executed with mode operated by RAM/ mode
operated by ROM.
• ROM writing can be executed for the data of MT Developer2.
SW8DNC-SV Q
—
QnUD(E)(H)CPU/QnUDVCPU
Combination with
Q173DCPU(-S1)/Q172D(-S1)CPU
Settable between CPU modules
Q173DCPU(-S1)/Q172DCPU(-S1)
D(P).DDRD, D(P).DDWR,
D(P).SFCS, D(P).SVST,
,
D(P).CHGT, D(P).CHGV,
,
D(P).CHGA, D(P).GINT
D(P).DDRD, D(P).DDWR,
D(P).SFCS, D(P).SVST,
D(P).CHGT, D(P).CHGV,
D(P).CHGA
Q172DLX, Q173DPX,
(Note-1)
Q173DSXY
Q172DLX, Q172DEX, Q173DPX,
(Note-1)
Q173DSXY
Q172DLX, Q173DPX
SW7DNC-SV Q
No restriction
Combination with
Q173DSCPU/Q172DSCPU
Provided
Possible
(Note-1): Q173DCPU-S1/Q172DCPU-S1 only
(Note-2): SV22 advanced synchronous control only
APP - 33
Q173HCPU/Q172HCPU
S(P).DDRD, S(P).DDWR,
S(P).SFCS, S(P).SVST,
S(P).CHGT, S(P).CHGV,
S(P).CHGA, S(P).GINT
S(P).DDRD, S(P).DDWR,
S(P).SFCS, S(P).SVST,
S(P).CHGT, S(P).CHGV,
S(P).CHGA
Interlock condition by the to self
CPU high speed interrupt accept
flag from CPU is necessary.
Q172LX, Q173PX
Q172LX, Q172EX, Q173PX
Q172LX, Q173PX
• QnUD(H)CPU is set to CPU
No.1.
• Q3 B can be used as a main
base unit.
• Q172LX, Q172EX and Q173PX
can be mounted to I/O 0 to 2 slot.
L.CLR switch
RUN/STOP switch
Rom writing is executed with
installation mode/ mode written in
ROM.
SW6RN-SV Q
SW5RN-SV Q
Qn(H)CPU
Install Motion CPU module on the
right-hand side of PLC CPU
module.
Combination with
Q173CPUN(-T)/Q172CPUN(-T).
Not settable between CPU
modules
None
Impossible