2 MULTIPLE CPU SYSTEM
2.3 Communication between the PLC CPU and the Motion CPU in the Multiple CPU System
2.3.1 CPU shared Memory
(1) Structure of CPU shared memory
The CPU shared memory is memory provided for each CPU module by which
data is written or read between CPU modules of a Multiple CPU system.
The CPU shared memory consists of four areas.
• Self CPU operation information area
• System area
• User setting area
• Multiple CPU high speed transmission area
The CPU shared memory configuration and the availability of the communication
from the self CPU using the CPU shared memory by program are shown below.
CPU shared memory
Self CPU operation
User setting area
Multiple CPU high speed
(Variable size in 0 to
14k[points]: 1k words in unit)
(Note-1) : Use the MULTW instruction to write to the user setting area of the self
CPU in the Motion CPU.
Use the S. TO instruction to write to the user setting area of the self CPU
in the PLC CPU.
(Note-2) : Use the MULTR instruction to read the shared memory of self CPU and
other CPU in the Motion CPU.
Use the FROM instruction/Multiple CPU area device (U \G ) to read the
shared memory of the Motion CPU from the PLC CPU.
(Note-3) : Refer to Section 2.3.2(1) for the access method of Multiple CPU high
speed transmission area.
: Communication allowed
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: Communication not allowed