Mitsubishi Electric Q Series Programming Manual page 68

2 MULTIPLE CPU SYSTEM
b) SV43
• Description of Multiple CPU area device
Word device : # Q
Bit device : # Q
(Example)
• Multiple CPU high speed transmission memory address of CPU
No.2: 10002
#Q1\2
• Bit 14 of CPU No.3 Multiple CPU high speed transmission
memory address 10200
#Q2\200.E
• Example of access in the program
<Motion program>
• Store K12345678 to the Multiple CPU high speed transmission
memory 10200,10201 of self CPU (CPU No.2).
#Q1\200:L = K12345678;
• Turn on bit 12 of the Multiple CPU high speed transmission
memory 10301 of self CPU (CPU No.3)
SET #Q2\301.C;
• Program which executes the positioning for Axis X to position set
in the Multiple CPU high speed transmission memory 10400,
10401 of CPU No.1 at the speed set in the 10402, 10403 of CPU
No.1, and uses bit 1 of CPU No.1 Multiple CPU high speed
transmission memory 10404 of CPU No.1 as a skip signal.
G32 X#Q0\400:L F#Q0\402:L SKIP #Q\404.1;
POINT
This method can be used to access only the Multiple CPU high speed transmission
area of CPU shared memory. It cannot be used to access the CPU shared memory
(0 to 4095).
\
CPU shared memory address (Decimal) (0 to up to 14335)
CPU No.
CPU No.
Set value
\ .
Bit specification (0 to F : Hexadecimal)
CPU shared memory address (Decimal) (0 to up to 14335)
CPU No.
CPU No.
Set value
(Note): Write the value that attracted 10000 from specified CPU
shared memory address.
(Accessible memory address : 10000 to 24335)
2 - 17
CPU No.1 CPU No.2 CPU No.3
0 1 2
CPU No.1 CPU No.2 CPU No.3
0 1 2
(Note)
CPU No.4
3
(Note)
CPU No.4
3