Infineon Technologies C166S V2 User Manual page 77

C-Flag V-Flag
0 0
0 1
1 0
1 1
For addition and subtraction with "Carry", the Z-flag is only set to 1 if the Z-flag already
contains a 1 as a result from previous operation and the result of the current ALU
operation also equals zero. This mechanism supports the multiple precision
calculations.
For Boolean bit operations with only one operand, the Z-flag represents the logical
negation of the previous state of the specified bit. For Boolean bit operations with two
operands, the Z-flag represents the logical NORing of the two specified bits. For the
Prioritize operation, the Z-flag indicates whether the second operand was zero or not.
• E-Flag: End of table flag. The E-flag can be altered by the instructions which perform
ALU or data movement operations. The E-flag is cleared by those instructions that
cannot be reasonably used for table search operations. In all other cases, the E-flag
value depends on the value of the source operand to signify whether the end of a
search table is reached or not. If the value of the source operand of an instruction
equals the lowest negative number which depends on the data format of the
corresponding instruction ('8000
type), the E-flag is set to 1; otherwise, it is cleared.
• MULIP-Flag: The MULIP-flag always sticks to 0.
Note: The MULIP flag is a part of the C166 task environment. For compatibility reasons,
the bit is still implemented even if not used. A multiply and divide ALU operation
of the C166S V2 CPU is no longer interruptible.
• BANK: The BANK bitfield of the PSW registers indicates which one of the three
physical register banks is activated. The BANK field is updated by hardware upon
entry into an interrupt service routine, but it can be also modified by software. The
BANK field can be changed explicitly by any instruction which can write to the PSW.
Also, it is implicitly updated by the RETI instruction.
• HLDEN: Refer to EBC
CPU Interrupt Status (IEN, ILVL)
The Interrupt Enable bit allows global enable (IEN=1) or disable (IEN=0) of interrupts.
The 4-bit Interrupt Level field (ILVL) specifies the priority of the current CPU activity. The
interrupt level is updated by hardware upon entry into an interrupt service routine, but it
can also be modified via software to prevent other interrupts from being acknowledged.
In case an interrupt level '15' has been assigned to the CPU, it has the highest possible
User Manual
Rounding Error Quantity
No rounding error
0 < Rounding error
Rounding error
Rounding error
' for the word data type, or '80
H
Chapter 6.4.1.
2-77
User Manual
C166S V2
Central Processing Unit
1
< /
2
1
= /
2
1
> /
2
' for the byte data
H
V 1.7, 2001-01
LSB
LSB
LSB