Infineon Technologies C166S V2 User Manual page 126

respective control registers. The two upper bits of the interrupt priority level are set to
'11 ', which limits the allowed interrupt priority level to be greater than or equal to 12.
B
FINT0CSP
Fast Interrupt Control Register 0
15 14 13 12
EN 0 0 GPX
rw r r
FINT1CSP
Fast Interrupt Control Register 1
15 14 13 12
EN 0 0 GPX
rw r r
Field
EN
GPX
ILVL
User Manual
11 10 9
ILVL GLVL
rw rw
11 10 9
ILVL GLVL
rw rw
Bits Type Description
[15] rw
[12] rw
[11:10] rw
Interrupt and Exception Handling
XSFR
8 7 6
rw
XSFR
8 7 6
rw
Fast Interrupt Enable
0 The interrupt jump table cache is disabled.
No fast interrupt is used.
1 The interrupt jump table cache is enabled.
A fast interrupt (direct jump to the interrupt
service routine) is used instead of the
normal fetch from the interrupt vector table.
Group Priority Extension
This bit enables group extension for fast interrupts.
(hardwired to 0 for fewer than 64 interrupt nodes)
Interrupt Priority Level
This bit field selects the lower two bits of the
interrupt priority level associated with this interrupt
jump table cache entry.
Note: The two upper bits of the interrupt priority
level are set to '11
interrupt priority level greater than or equal
to 12.
5-126
User Manual
Reset Value: 0000
5 4 3 2
SEG
rw
Reset Value: 0000
5 4 3 2
SEG
rw
', which ends in an
B
V 1.7, 2001-01
C166S V2
H
1 0
H
1 0