Infineon Technologies C166S V2 User Manual page 137

The Parity Fault is an asynchronous external event while all other Class B traps are
generated in the pipeline during the execution of instructions. It is not possible for two
different instructions in the pipeline to generate Class A and Class B traps in the same
CPU cycle. Class B trap events can be generated only during memory stage execution.
Instructions which caused a Class B trap event are always executed. In the case of a
class B trap, the pipeline is directly canceled and the IP of the instruction following the
one which caused the trap is pushed on the stack. Therefore, the stack always contains
the IP of the first following not-executed instruction in the instruction flow.
Note: The Branch Folding Unit allows the execution of branch instructions in parallel with
the preceding instruction. The pre-processed branch instruction is combined with
the preceding instruction. The branch is executed together with the instruction
causing the Class B trap. The IP of the first following not-executed instruction in
the instruction flow is pushed into the stack.
During execution of a Class A trap service routine, any Class B trap will not be serviced
until the Class A trap service routine is exited with a RETI instruction. In this case, the
Class B trap condition is stored in the TFR register, but the IP value of the instruction
which caused this trap will be lost.
Note: If a Class A trap occurs simultaneously with a Class B trap, both trap flags are set.
The IP of the instruction following the one which caused the trap is pushed into the
stack, and the Class A trap is executed. If this occurs during execution of an
atomic/extend sequence or I/O read access in progress, then the presence of the
Class B trap breaks the protection of atomic/extend operations and the class A
trap will be executed immediately without waiting for the sequence completion.
After return from the service routine, the IP is popped from the system stack and
immediately pushed again because of the other pending Class B trap. In this
situation, the restoration of the interrupted instruction flow is not possible.
• External NMI Trap: Whenever a high to low transition on the dedicated external NMI
pin (Non-Maskable Interrupt) is detected, the NMI flag in register TFR is set and the
CPU will enter the NMI trap routine.
• Stack Overflow Trap: Whenever the stack pointer is implicitly decremented and the
stack pointer is equal to the value in the stack overflow register STKOV, the STKOF
flag in register TFR is set and the CPU will enter the stack overflow trap routine.
• Stack Underflow Trap: Whenever the stack pointer is implicitly incremented and the
stack pointer is equal to the value in the stack underflow register STKUN, the STKUF
flag is set in register TFR, and the CPU will enter the stack underflow trap routine.
• Software Break Trap: When the instruction currently being executed by the CPU is
a SBRK instruction, the SOFTBRK flag is set in register TFR and the CPU enters the
software break debug routine. The flag generation of the software break instruction
can be disabled by an On-chip Emulation Module. In this case, the instruction only
breaks the instruction flow and signals this event to the debugger. The flag is not set
and the trap will not be executed.
User Manual
Interrupt and Exception Handling
5-137
User Manual
C166S V2
V 1.7, 2001-01