Infineon Technologies C166S V2 User Manual page 119

Interrupt
Request
Lines
irq0
irq1
irq2
irq3
irq n-3
1)
irq n-2
1) number of interrupt nodes n (upto 128)
2)
End of PEC Interrupt (EOPINT) is connected to interrupt request line irq n-1.
Therefore, only n-1 interrupt lines (irq n-2...0) are available for peripheral request
handling.
Figure 5-1 Block Diagram of the Interrupt and PEC Controller
User Manual
Interrupt and Peripheral Event Controller
SRCP0
SRCP1
SRCP7
Arbitration
Arbitr.
Winner Peripheral
Event
Controller
(PEC)
EOP
irq n-1
INT 2)
Arbitration PEC
Control Control
(Interrupt (PEC
Control Control
Registers) Registers)
irq0IC PECC0
irq1IC PECC1
irq126IC PECC7
EOPIC PECISNC
Interrupt and Exception Handling
PEC Pointer
DSTP0 PECSEG0
DSTP1 PECSEG1
DSTP7 PECSEG7
PEC Request
Request Request
Control Control
Interrupt
Handler
Interrupt Interrupt
Request Request
Interrupt
Handler
Control
Fast Bank
Switching
BNKSEL0
BNKSEL3
Interrupt Jump
Table Cache
FINT0CSP
FINT0ADDR
FINT1CSP
FINT1ADDR
5-119
User Manual
C166S V2
C166S V2
CPU
Injection
Control
(CPU Action
Request)
OCE/
OCDS
OCE
Injection
Request &
Control
V 1.7, 2001-01