Infineon Technologies C166S V2 User Manual page 251

EXTP
Group
Syntax
Source Operand(s)
Destination Operand(s)
Operation
(count) ← (op2) [1 ≤ op2 ≤ 4]
Disable interrupts and Class A traps
Data_Page ← (op1)
DO WHILE ((count) ≠ 0 AND Class_B_Trap_Condition ≠ TRUE)
END WHILE
(count) ← 0
Data_Page ← (DPPx)
Enable interrupts and traps
Description
Overrides the standard DPP addressing scheme of the long and indirect addressing
modes for a specified number of instructions. During their execution, both standard and
PEC interrupts and class A hardware traps are locked. The EXTP instruction becomes
active immediately such that no additional NOPs are required. For any long ('mem') or
indirect ([...]) address in the EXTP instruction sequence, the 10-bit page number
(address bits A23-A14) is not determined by the contents of a DPP register, but by the
value of op1 itself. The 14-bit page offset (address bits A13-A0) is derived from the long
or indirect address as usual. The value of op2 defines the length of the affected
instruction sequence.
CPU Flags
E Not affected.
Z Not affected.
V Not affected.
C Not affected.
N Not affected.
User Manual
Begin EXTended Page Sequence
System Control Instructions
EXTP op1, op2
op1 → 10-bit page number
op2 → 2-bit instruction counter
none
Next Instruction
(count) ← (count) - 1
E Z
- -
Detailed Instruction Description
V C
- -
8-251
User Manual
C166S V2
EXTP
N
-
V 1.7, 2001-01