Infineon Technologies C166S V2 User Manual page 112

• The CSFR result registers MDH, MDL, MSW, MAH, MAL, MRW of the ALU and MAC-
Unit are updated late in the Execute stage of the pipeline. If an instruction (except
CoSTORE) accesses explicitly these registers in the memory stage, the value cannot
be forwarded. The instruction must be stalled for one cycle on the Memory stage.
I ........
n-1
I MUL R0,R1
n
I MOV R6,MDL
n+1
I ADD R6,R1
n+2
I MOV R3,[R0]
n+3
I ........
n+4
T
n
DECODE I =
n
MUL R0,R1
ADDRESS I
n-1
MEMORY I
n-2
EXECUTE I
n-3
WRITE BACK I
n-4
By reordering instructions, the bubble in the pipeline can be filled with an instruction not
using this resource.
I ........
n-1
I MUL R0,R1
n
I MOV R3,[R0]
n+1
I MOV R6,MDL
n+2
I ADD R6,R1
n+3
I ........
n+4
T
n
DECODE I =
n
MUL R0,R1
I
ADDRESS
n-1
MEMORY I
n-2
EXECUTE I
n-3
WRITE BACK I
n-4
User Manual
T T
n+1 n+2
I = I =
n+1 n+2
MOV R6,MDL ADD R6,R1
I = I =
n n+1
MUL R0,R1 MOV R6,MDL
I I =
n-1 n
MUL R0,R1
I I
n-2 n-1
I I
n-3 n-2
T T
n+1 n+2
I = I =
n+1 n+2
MOV R3,[R0] MOV R6,MDL
I = I =
n n+1
MUL R0,R1 MOV R3,[R0]
I I =
n-1 n
MUL R0,R1
I I
n-2 n-1
I I
n-3 n-2
4-112
Instruction Pipeline
T T
n+3 n+4
I = I =
n+3 n+3
MOV R3,[R0] MOV R3,[R0]
I = I =
n+2 n+2
ADD R6,R1 ADD R6,R1
I = I =
n+1 n+1
MOV R6,MDL MOV R6,MDL
I =
n
MUL R0,R1
I I =
n-1 n
MUL R0,R1
T T
n+3 n+4
I = I
n+3 n+4
ADD R6,R1
I = I =
n+2 n+3
MOV R6,MDL ADD R6,R1
I = I =
n+1 n+2
MOV R3,[R0] MOV R6,MDL
I = I =
n n+1
MUL R0,R1 MOV R3,[R0]
I I =
n-1 n
MUL R0,R1
User Manual
C166S V2
T
n+5
I
n+4
I =
n+3
MOV R3,[R0]
I =
n+2
ADD R6,R1
I =
n+1
MOV R6,MDL
T
n+5
I
n+5
I
n+4
I =
n+3
ADD R6,R1
I =
n+2
MOV R6,MDL
I =
n+1
MOV R3,[R0]
V 1.7, 2001-01