Infineon Technologies C166S V2 User Manual page 247

DIVLU
Group
Syntax
Source Operand(s)
Destination Operand(s)
Operation
(MDL) ← (MD) / op1
(MDH) ← (MD) mod (op1)
Description
Performs an extended unsigned 32-bit by 16-bit division of the two words stored in the
MD register by the source word operand op1. The unsigned quotient is then stored in
the low order word of the MD register (MDL) and the remainder is stored in the high
order word of the MD register (MDH).
CPU Flags
E Always cleared.
Z Set if quotient, stored in the MDL register, equals zero. Cleared
otherwise. Undefined if the V flag is set.
V Set if an arithmetic overflow occurred, i.e. the quotient cannot be
represented in a word data type, or if the divisor op1 was zero. Cleared
otherwise.
C Always cleared.
N Set if the most significant bit of the quotient, stored in the MDL register, is
set. Cleared otherwise. Undefined if the V flag is set.
Encoding
Mnemonic
DIVLU Rw
User Manual
32-by-16 Unsigned Division
Arithmetic Instructions
DIVLU op1
op1 → WORD
MD → DOUBLEWORD
MD → DOUBLEWORD
E Z
0 *
n
Detailed Instruction Description
V C
* 0
Format
7B nn
8-247
User Manual
C166S V2
DIVLU
N
*
Bytes
2
V 1.7, 2001-01