Infineon Technologies C166S V2 User Manual page 109

• Bandwidth conflicts in the DPRAM Area
The CoXXX instructions are the only instructions able to read two memory operands
per cycle. A conflict between the two read and one pending write access can
occur if all three operands are located in the DPRAM areas. This is especially
important for performance in the case of executing a filter routine. One of the operands
should be located in the internal SRAM to guarantee a single cycle execution time of
the CoXXX instructions.
I ........
n-1
I ADD op1,R1
n
I ADD R6,R0
n+1
I CoMAC [IDX0],[R0]
n+2
I MOV R3,[R0]
n+3
I .......
n+4
.
T
n
DECODE I =
n
ADD op1,R1
ADDRESS I
n-1
MEMORY I
n-2
EXECUTE I
n-3
WRITE BACK I
n-4
User Manual
T T
n+1 n+2
I = I =
n+1 n+2
ADD R6,R0 CoMAC .....
I = I =
n n+1
ADD op1,R1 ADD R6,R0
I I =
n-1 n
ADD op1,R1
I I
n-2 n-1
I I
n-3 n-2
4-109
Instruction Pipeline
T T
n+3 n+4
I = I
n+3 n+4
MOV R3,[R0]
I = I =
n+2 n+3
CoMAC ..... MOV R3,[R0]
I = I =
n+1 n+2
ADD R6,R0 CoMAC .....
I = I =
n n+1
ADD op1,R1 ADD R6,R0
I I =
n-1 n
ADD op1,R1
User Manual
C166S V2
T
n+5
I
n+4
I =
n+3
MOV R3,[R0]
I =
n+2
CoMAC .....
I =
n+1
ADD R6,R0
V 1.7, 2001-01