Infineon Technologies C166S V2 User Manual page 193

Notes on CoXXX instructions
All CoXXX instructions have a 3-bit wide extended control field 'rrr' in the operand field
to control the MRW repeat counter. It is located within the CoXXX instructions at bit
positions [31:29].
– '000' -> regular CoXXX instruction.
– '001' -> RESERVED
– '010' -> '- USR0 CoXXX' instruction.
– '011' -> '- USR1 CoXXX' instruction.
– '1xx' -> RESERVED.
Notes on CoXXX instructions using indirect addressing modes
These CoXXX instructions have extended control fields in the operand field to specify
the special indirect addressing mode.
Bitfield 'X' is 4-bits wide and is located within CoXXX instructions at bit positions [15:12].
Bit [15] specifies one of the two IDX address pointers; the bitfield [14:12] specifies the
operation concerning the IDX pointer.
Bit[15]:
– '0' -> IDX0
– '1' -> IDX1
Bitfield[14:12]
– '000' -> RESERVED
– '001' -> no-operation
– '010' -> IDX +2
– '011' -> IDX -2
– '100' -> IDX + QX0
– '101' -> IDX - QX0
– '110' -> IDX + QX1
– '111' -> IDX - QX1
Bitfield 'qqq' is 3-bits wide and is located within CoXXX instructions at bit positions
[26:24]. It specifies the operation concerning the Rw pointer.
Bitfield[26:24]
– '000' -> RESERVED
– '001' -> no-operation
– '010' -> Rw +2
– '011' -> Rw -2
– '100' -> Rw + QR0
– '101' -> Rw - QR0
– '110' -> Rw + QR1
– '111' -> Rw - QR1
User Manual 7-193
User Manual
C166S V2
Instruction Set
V 1.7, 2001-01