Infineon Technologies C166S V2 User Manual page 156

Figure 6-3 Multiplexed Bus Read
ALE
ADDR, CS
RD
read DATA
clocks
needed bits
Figure 6-4 Multiplexed Bus Write
ALE
ADDR, CS
WR
write DATA
clocks
needed bits
• a phase: addresses valid, ALE high, no command. CS switch tristate wait states
• b phase: addresses valid, ALE high, no command. ALE length
• c phase: addresses valid, ALE low, no command. Address hold, R/W delay
• d phase: address tristate for read cycles, data valid for write cycles, ALE low, no
command
• e phase: command (read or write) active. Access time
• f phase: command inactive, address hold. Read data tristate time, write data hold
time.
User Manual
a b c d
addr valid
0-1
0-3 1-2 0-3
2
2 1 1
a b c d
address valid
0-3 0-1
1-2
0-3
2
1
2 1
6-156
External Bus Controller
e f
valid
data in valid
1-32 0-3
5 2rd
e f
valid
data out valid
1-32 0-3
5 2wr
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V 1.7, 2001-01