Infineon Technologies C166S V2 User Manual page 101

Mapping of the global General Purpose Registers to DPRAM Addresses is shown here:
DPRAM Address
<CP> + 1E
H
<CP> + 1C
H
<CP> + 1A
H
<CP> + 18
H
<CP> + 16
H
<CP> + 14
H
<CP> + 12
H
<CP> + 10
H
<CP> + 0E
H
<CP> + 0C
H
<CP> + 0A
H
<CP> + 08
H
<CP> + 06
H
<CP> + 04
H
<CP> + 02
H
<CP> + 00
H
A particular Switch Context (SCXT) instruction performs register bank switching and an
automatic save of the previous context. The number of implemented register banks
(arbitrary sizes) is limited only by the size of the available DPRAM.
The memory mapped GPRs use a block of sixteen consecutive words within DPRAM
Segment 0. The Context Pointer (CP) register determines the base address of the
currently active register bank. This register bank may consist of up to sixteen word GPRs
(R0, R1, .. R15), and/or of up to sixteen byte GPRs (RL0, RH0, º, RL7, RH7). The sixteen
byte GPRs are mapped onto the first eight word GPRs (see table above).
In contrast to the system stack, a register bank grows from lower towards higher address
locations and occupies a maximum space of 32 bytes. The GPRs are accessed via short
2-, 4- or 8-bit addressing modes using the Context Pointer (CP) register as base address
(independent of the current DPP register contents). Additionally, each bit in the currently
active register bank can be accessed individually.
User Manual
Byte Registers
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RH7RL7
RH6RL6
RH5RL5
RH4RL4
RH3RL3
RH2RL2
RH1RL1
RH0RL0
3-101
C166S V2 Memory Organization
Word Register
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
User Manual
C166S V2
V 1.7, 2001-01