Infineon Technologies C166S V2 User Manual page 148

Field
SRCSEGx
DSTSEGx
• PEC channel is enabled
a) Control bit EOPINT = 0 or 1
ACTIONS:
– PEC request is proceeded
– No other interrupt activity
• PEC channel is enabled and the bit field COUNT gets a decrement from '01
triggered by a service request.
a) Control bit EOPINT = 0 (compatible with C166)
ACTIONS:
– PEC request is proceeded
– Interrupt request flag (xxIR) of the requesting interrupt node (arbitration winner) is
not cleared, participates on the next arbitration cycle, and triggers a normal interrupt
on the same level as the PEC request is served.
b) Control bit EOPINT = 1 (enhanced end of PEC interrupt feature)
ACTIONS:
– PEC request is proceeded
– Interrupt request flag (xxIR) of requesting interrupt node (arbitration winner) is
cleared and will not trigger more actions.
– Interrupt request flag of the end of PEC interrupt subnode will be set
(PECISNC.CxIR = 1)
– If the respective interrupt enable flag of the end of PEC interrupt subnode was set
before by software (PECISNC.CxIE = 1), an end of PEC interrupt is requested
(EOPIC.EOPIR = 1). This end of PEC interrupt participates on the next arbitration
cycle with its priority (selected via EOPIC.ILVL and EOPIC.GLVL), if this interrupt
source was enabled before by software (EOPIC.EOPIR = 1). With this behavior, an
end of PEC interrupt can be triggered on a level lower than the respective PEC
requests have been serviced.
• PEC channel is disabled if the bit field COUNT is cleared (either by hardware or by
software).
1)
Every PEC channel is automatically enabled when its COUNT value is greater than 00
User Manual
Bits Type Description
[15:8] rw Source Pointer Segment Address of Channel x
Source Address bits 23-16
[7:0] rw Destination Pointer Segment Address of
Channel x
Destination Address bits 23-16
1)
and the bit field COUNT has a value higher than '01
Interrupt and Exception Handling
5-148
User Manual
C166S V2
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H
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V 1.7, 2001-01