Infineon Technologies C166S V2 User Manual page 47

be addressed via 'reg'. Note that the high byte of an SFR cannot be accessed
via the 'reg' addressing mode. Short 'reg' addresses in the range from F0
FF always specify GPRs. In that case, only the lower four bits of 'reg' are sig-
H
nificant for physical address generation and, therefore, it is identical to the
address generation described for the 'Rb' and 'Rw' addressing modes.
bitoff: Specifies direct access to any word in the bit addressable memory space. The
'bitoff' value requires eight bits in the instruction format. Depending on the
specified 'bitoff' range different base addresses are used to generate physical
addresses: Short 'bitoff' addresses in the range from 00
00'FD00
H
locations in the range from 00'FD00
the range from 80
SFR word locations in the range from 00'FF00
00'F100
H
00'F100
H
ceding EXT*R instruction to switch the base address. For short 'bitoff'
addresses from F0
address of the selected word GPR.
bitaddr: Any bit address is specified by a word address within the bit addressable
memory space (see 'bitoff'), and by a bit position ('bitpos') within that word.
Therefore, 'bitaddr' requires twelve bits in the instruction format.
User Manual
as a base address to specify the 128 highest internal RAM word
to EF use base address 00'FF00
H H
to specify the internal ESFR word locations in the range from
to 00'F1DE . The 'bitoff' accesses to the ESFR area require a pre-
H
to FF , only the lowest four bits are used to generate the
H H
h to 00'FDFE
H H
to 00'FFDE
H
2-47
User Manual
C166S V2
Central Processing Unit
to 7F use
H H
. Short 'bitoff' addresses in
to specify the internal
H
or base address
H
V 1.7, 2001-01
to
H