Infineon Technologies C166S V2 User Manual page 194

Notes on the Undefined Opcodes
A hardware trap occurs when one of the undefined opcodes signified by '----' is decoded
by the CPU.
In the following table used symbols for instruction cycle times:
reg 1 cycle, if short register addressing uses GPR
2 cycles, else
bit 1 cycle if at least one bit address is a GPR
2 cycles, else
co 1 to 2 cycle (see table for MAC instructions)
0-1 0 cycles, if branch is executed zerocycle
1 cycle, else
2-3 2 cycles, if CPUCON1.SGTDIS = 1
3 cycles, else
5-6 5 cycles, if CPUCON1.SGTDIS = 1
6 cycles, else
4+15 4 visible cycles to calculate PSW for division,
plus 15 invisible cycle where the result is not available
1-31 1 to 31 cycles for 'multicycle' NOP (opcode CC 000d:dddd)
User Manual 7-194
User Manual
C166S V2
Instruction Set
V 1.7, 2001-01