Infineon Technologies C166S V2 User Manual page 410

CoSHR
Group
Syntax
Source Operand(s)
Destination Operand(s)
Operation
(count) ← (op1)
(C) ← 0
DO WHILE (count) ≠ 0
END WHILE
Description
Shifts the 40-bit ACC register contents right the number of times as specified by the
operand op1. The most significant bits of the result are filled with zeros accordingly.
Only shift values from 0 to 16 (inclusive) are allowed. op1 can be either a 5-bit unsigned
immediate data (the shift range is from 0 to 16 in this case) or the four least significant
bits (the shift range is from 0 to 15 in that case) of any register directly or indirectly
addressed operand. The MS bit of the MCW register does not affect the result.
MAC Flags
MV MSL
0 -
MV Always cleared.
MSL Not affected.
ME Set if the MAE is used. Cleared otherwise.
MSV Not affected.
MC Always cleared.
MZ Set if result equals zero. Cleared otherwise.
MN Set if the most significant bit of the result is set. Cleared otherwise.
User Manual
Accumulator Logical Shift Right
Shift Instructions
CoSHR op1
op1 → 5-bit unsigned data
ACC → 40-bit signed value
((ACC[n]) ← (ACC[n+1]) [n=0...38]
(ACC[39]) ← 0
(count) ← (count) -1
ME MSV
* -
Detailed Instruction Description
MC MZ
0 *
8-410
User Manual
C166S V2
CoSHR
MN Sat.
* no
V 1.7, 2001-01