Infineon Technologies C166S V2 User Manual page 44

If the interrupt occurred before the load phase, the entire validation process is restarted
from the very beginning. If the store phase has been completed before the interrupt, only
the load phase is executed.
global
Bank
Execution
Task A
Interrupt of Task B
Execution of
SCXT CP
Register Bank
validation
process
started
Note: Validation Process and Hardware Interrupts using a Local Register Bank
Note: A cache validation process of Task A can be interrupted by a Task B which uses
a local register bank. Task B itself is interrupted again by an interrupt Task C which
uses a global register bank again. In this case, the validation process of Task A
must be finished before code of Task C can be executed. This means that the
validation process of Task A does not affect the interrupt latency of Task B but the
latency of Task C. If Task C would immediately interrupt Task A, the register bank
validation process of Task A would be finished first. The worst case interrupt
latency is identical in both cases (see
.
global
Bank
Execution
Task A
Interrupt of Task B
Execution of
SCXT CP
Register Bank
validation
process
started
Figure 2-13 Validation Process and Hardware Interrupts using Local and Global
Register Bank
User Manual
recognized
stopped
local
Bank
Execution
Task B
Interrupt of Task C
recognized
recognized
stopped
local
Bank
Execution
Task B
Execution of
Figure 2-12 and
global
Bank
Execution
Task C
Execution of
RETI
Register Bank
validation
process
restarted finished
2-44
User Manual
C166S V2
Central Processing Unit
global
Bank
Execution
RETI
Register Bank
validation
process
restarted finished
Figure 2-13).
local
Bank
Execution
Task B
Execution of
RETI
V 1.7, 2001-01
Task A
global
Bank
Execution
Task A