Infineon Technologies C166S V2 User Manual page 220

ATOMIC
Group
Syntax
Source Operand(s)
Destination Operand(s)
Operation
(count) ← (op1) [1
Disable interrupts and Class A traps
DO WHILE ((count) ≠ 0 AND Class_B_Trap_Condition ≠ TRUE)
END WHILE
(count) ← 0
Enable interrupts and traps
Description
Causes standard and PEC interrupts and class A hardware traps to be disabled for a
specified number of instructions. The ATOMIC instruction becomes immediately active.
No NOPs are required for normal ATOMIC execution. Depending on the value of op1,
the period of validity of the ATOMIC sequence extends over the sequence of the next
one to four instructions being executed after the ATOMIC instruction. All instructions
requiring multiple cycles or hold states to be executed are regarded as one instruction
in this sense. Any instruction type can be used with the ATOMIC instruction.
CPU Flags
E Not affected.
Z Not affected.
V Not affected.
C Not affected.
N Not affected.
Encoding
Mnemonic
ATOMIC #irang2
User Manual
Begin ATOMIC Sequence
System Control Instructions
ATOMIC op1
op1 → 2-bit instruction counter
none
≤ ≤
op1
Next Instruction
(count) ← (count) - 1
E Z
- -
Detailed Instruction Description
4]
V C
- -
Format
D1 :00##-0
8-220
User Manual
C166S V2
ATOMIC
N
-
Bytes
2
V 1.7, 2001-01