Infineon Technologies C166S V2 User Manual page 72

seventeen CPU cycles, while further instructions are executed in parallel. If another
instruction tries to use the unit while a division is still running, the execution of this new
instruction is stalled until the division is finished.
Interrupt tasks can also be started and executed immediately without any delay. The
previous division will be finished in the background. If an instruction of the interrupt task
uses the multiply and divide unit before the previous division process is finished, the
instruction flow will be stalled as well. To avoid these stalls, the multiply and division unit
should not be used during the first fourteen CPU cycles of the interrupt tasks. This
requires up to fourteen one-cycle instructions to be executed between the interrupt entry
and the first instruction which uses the multiply and divide unit again (worst case).
The Multiply/Divide High Register MDH
The sixteen bit, non-bit addressable MDH register contains the high word of the 32-bit
multiply/divide MD register used by the CPU when it performs a multiplication or a
division using implicit addressing (DIV, DIVL, DIVLU, DIVU, MUL, MULU). After an
implicitly addressed multiplication, this register represents the high order sixteen bits of
the 32-bit result. For long divisions, the MDH register must be loaded with the high order
sixteen bits of the 32-bit dividend before the division has started. After any division, the
MDH register represents the 16-bit remainder.
MDH
Multiply Divide High Word
15 14 13 12
Field
MDH
Whenever this register is updated via software, the Multiply/Divide Register In Use
(MDRIU) flag in the Multiply/Divide Control register (MDC) is set to 1.
The Multiply/Divide Low Register MDL
The sixteen bit, non-bit addressable MDL register contains the low word of the 32-bit
multiply/divide MD register used by the CPU when it performs a multiplication or a
division using implicit addressing (DIV, DIVL, DIVLU, DIVU, MUL, MULU). After a
User Manual
11 10 9
Bits Type Description
[15:0] rwh High part of MD
The high order sixteen bits of the 32-bit multiply and
divide register MD.
SFR
8 7 6 5
MDH
rwh
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User Manual
C166S V2
Central Processing Unit
Reset Value: 0000
4 3 2 1
V 1.7, 2001-01
H
0