Infineon Technologies C166S V2 User Manual page 35

User Manual
C166S V2
Central Processing Unit
The register file is split into three independent physical register banks. Because of
behavior differences, the banks can be distinguished as global and local register banks.
There are two local and one global register bank.
The memory-mapped GPR bank selected by the current CP is always cached in the
global register bank. Only one memory-mapped GPR bank can be cached at the time.
In the case of a context switch, the cache contents must be sequentially saved and
restored.
Note: The global register bank is the equivalent of the memory-mapped GPR bank of the
C166 family which is selected by the context pointer CP.
To support a very fast context switch for time-critical tasks, two independent not memory
mapped GPR banks are available. They are physically and logically located in the two
special local register banks. They cannot be accessed via a 24-bit physical memory
address.
Only one of the three physical register banks can be activated at the same time. The
bank selection is controlled by the BANK bitfield of the PSW. The BANK bitfield can be
changed explicitly by any instruction which writes to the PSW, or implicitly by a RETI
instruction, an interrupt or hardware trap. In case of an interrupt, the selection of the
register bank is configured in the Interrupt Controller ITC. Hardware traps always use the
global register bank.
User Manual 2-35 V 1.7, 2001-01