Infineon Technologies C166S V2 User Manual page 258

EXTSR
Begin EXTended Segment and Register Sequence
Group
Syntax
Source Operand(s)
Destination Operand(s)
Operation
(count) ← (op2) [1 ≤ op2 ≤ 4]
Disable interrupts and Class A traps
Data_Segment ← (op1)
SFR_range ← Extended
DO WHILE ((count) ≠ 0 AND Class_B_Trap_Condition ≠ TRUE)
END WHILE
(count) ← 0
Data_Page ← (DPPx)
SFR_range ← Standard
Enable interrupts and traps
Description
Overrides the standard DPP addressing scheme of the long and indirect addressing
modes and causes all SFR or SFR bit accesses via the 'reg', 'bitoff' or 'bitaddr'
addressing modes being made to the Extended SFR space for a specified number of
instructions. During their execution, both standard and PEC interrupts and class A
hardware traps are locked. The EXTSR instruction becomes immediately active such
that no additional NOPs are required. For any long ('mem') or indirect ([...]) address in
an EXTSR instruction sequence, the value of op1 determines the 8-bit segment
(address bits A23-A16) valid for the corresponding data access. The long or indirect
address itself represents the 16-bit segment offset (address bits A15-A0). The value of
op2 defines the length of the affected instruction sequence.
CPU Flags
E Not affected.
Z Not affected.
User Manual
System Control Instructions
EXTSR op1, op2
op1 → segment number
op2 → 2-bit instruction counter
none
Next Instruction
(count) ← (count) - 1
E Z
- -
Detailed Instruction Description
V C
- -
8-258
User Manual
C166S V2
EXTSR
N
-
V 1.7, 2001-01