Infineon Technologies C166S V2 User Manual page 29

Field
IP
0
The Code Segment Pointer CSP
This non-bit addressable register selects the code segment being used at run-time to
access instructions. The lower 8 bits of register CSP select one of up 256 segments of
64 Kilobytes each, while the higher 8 bits are reserved for future use. The reset value is
specified by the contents of the VECSEG register
CSP
Code Segment Pointer
15 14 13 12
0 0 0
r r r
Field
SEGNR
The actual code memory address is generated by direct extension of the 16-bit contents
of the IP register by the lower byte of the CSP register as shown in the figure below. The
CSP register can be only read and may not be written by data operations.
There are two modes: segmented and non-segmented. The mode is selected with the
SGTDIS bit in the CPUCON1 register. After reset, the segmented mode is selected.
CPUCON1
CPU Control Register 1
15 14 13 12
0 0 0
r r
r
Note: For a summary of the CPUCON1 register, please refer to
User Manual
Bits Type Description
[15:1] h Specifies the intra segment offset from which the
current instruction is to be fetched. IP refers to the
current segment <SEGNR>.
[0] - IP is always word-aligned
11 10 9
0 0 0 0
r r r r
Bits Type Description
[7:0] rh Specifies the code segment from which the current
instruction is to be fetched.
11 10 9
0 0 0 0
r r r r
(Section
SFR
8 7 6 5
0
r
SFR
8 7 6 5
0 0 VECSC
r rw
r
2-29
User Manual
C166S V2
Central Processing Unit
5.1.4).
Reset Value: 0000
4 3 2
SEGNR
rh
Reset Value: 0000
4 3 2
WDT SGT INT
CTL DIS SCXT
rw rw rw
Section 2.3.6.
V 1.7, 2001-01
H
1 0
H
1 0
BP ZCJ
rw rw