Infineon Technologies C166S V2 User Manual page 179

Table 7-1 shows the various combinations of pointer post-modification for the
addressing modes of the CoXXX instructions. The symbols "[Rw
used to refer to these addressing modes.
Table 7-1 Pointer Post-Modification Combinations for IDXi and Rwn
Symbol
⊗]" stands for
"[IDX
i
⊗]" stands for
"[Rw
n
Multiply and Divide Operations
The MDL and MDH registers are implicit source and/or destination operands of the
multiply and divide instructions.
Branch Target Addressing Modes
caddr: – Direct 16-bit jump target address (Updates the Instruction Pointer)
seg: – Direct 2-bit segment address
(Updates the Code Segment Pointer)
rel: – Signed 8-bit jump target word offset address relative to the Instruction
Pointer of the following instruction
#trap7: – Immediate 7-bit trap or interrupt number.
User Manual
Mnemonic Address Pointer Operation
[IDX ] (IDX
i
+]
[IDX (IDX
i
[IDX -] (IDX
i
+ QX
[IDX ] (IDX
i j
[IDX - QX ] (IDX
i j
(Rwn) ← (Rwn) (no-operation)
[Rwn]
(Rwn) ← (Rwn) +2 (n=0-15)
[Rwn+]
(Rwn) ← (Rwn) -2 (n=0-15)
[Rwn-]
(Rwn) ← (Rwn) + (QR
[Rwn+QR ]
j
(Rwn) ← (Rwn) - (QR
[Rwn - QR ]
j
7-179
n*
) ← (IDX
) (no-operation)
i i
) ← (IDX
) +2 (i=0,1)
i i
) ← (IDX
) -2 (i=0,1)
i i
) ← (IDX
) + (QX ) (i, j =0,1)
i i j
) ← (IDX
) - (QX ) (i, j =0,1)
i i j
j
) (n=0-15; j =0,1)
j
User Manual
C166S V2
Instruction Set
∗]" and "[IDX ∗]" will be
i
) (n=0-15;j =0,1)
V 1.7, 2001-01