Infineon Technologies C166S V2 User Manual page 33

Field Bits
2)
FASTBL [2]
SL [0]
1)
enables dedicated stall debug instructions:
STALLAM d ,h ,d
a a m
STALLEW d ,h ,d
e e w
Stalls the corresponding pipeline stage after d cycles for h cycles.
2)
The FASTBL bit is implemented, but reserved. So do not use it. The block feature is implemented in the CPU,
but not used by the Interrupt and Injection Unit.
Note: Register CPUCON2 is changeable in supervisor mode only. Supervisor mode is
finished by executing the EINIT instruction.
User Manual
Type Description
rw Enables the fast injection of block transfers
0
1
rw Enables short loop mode
0
1
,h Opcode: 44 d
m a
,h Opcode: 45 d
w e
Direct injection disabled
Direct injection enabled
Short loop mode disabled
Short loop mode enabled
h d h
a m m
h d h d and h are 6 bit each
e w w
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User Manual
C166S V2
Central Processing Unit
V 1.7, 2001-01