Infineon Technologies C166S V2 User Manual page 121

Interrupt
Request
Lines
Request
Lines
Arbitration
Stage 1:
Compared 4-bit ILVL+ 2/3-bit XGLVL
priority levels of interrupt sources
(64/128 priority levels)
Figure 5-2 Interrupt Arbitration
The first arbitration stage compares the priority levels of interrupt request lines. The
priority level of each requestor consists of interrupt priority level and group priority level.
An interrupt priority level is programmed for each interrupt request line by the 4-bit bit
field ILVL of the respective xxIC register. The group priority level is programmed for each
interrupt request line by the 2-bit bit field GLVL—and, in the case of more than 64
interrupt nodes, by the extension bit GPX of the register xxIC. GPX and GLVL combined
form the 3-bit (extended) group priority level XGLVL, controlling up to eight interrupt sub-
priorities within one of the sixteen interrupt levels.
Note: All interrupt request sources that are enabled and programmed to the same
interrupt priority level (ILVL) must have different group priority levels. Otherwise,
an incorrect interrupt vector may be generated.
The second arbitration stage compares the priority of the first stage winner with the
priority of OCDS service requests. C166S V2 OCDS service requests bypass the first
stage of arbitration and go directly to the CPU Action Control Unit. The CPU Action
Control Unit disregards the group priority level of interrupt/PEC requests and deals only
with interrupt priority levels (ILVL). For comparison with an OCDS service request priority
programmed with a 5-bit value, the 4-bit ILVL of the interrupt/PEC request is extended
to a 5-bit value with MSB=0. This means that any OCDS request with MSB=1 will always
User Manual
Interrupt
Arbitration
OCDS
or
OCE
xxxx (ILVL) +
x.xx (XGLVL)
PEC/
Interrupt
Handler
4-bit IRQ/PEC priority level
compared with
5-bit OCDS priority level
Interrupt and Exception Handling
OCDS break
request
xxxxx
(OCDS service
request priority
level)
CPU
0xxxx
Action
(ILVL
Control
extended with
0 in MSB)
Stage 2:
5-121
User Manual
C166S V2
Hardware
Traps
xxxxx
(request
priority level)
Arbitration
0xxxx
(ILVL. PSW
extended with
0 in MSB)
PSW
Stage 3:
5-bit request priority level
compared with
4-bit PSW priority level
V 1.7, 2001-01
CPU
CPU