Infineon Technologies C166S V2 User Manual page 155

Figure 6-1 Demultiplexed Bus Read
ALE
ADDR, CS
RD
read DATA
clock cycles
needed bits
Figure 6-2 Demultiplexed Bus Write
ALE
ADDR, CS
WR
write DATA
clock cycles
needed bits
• a phase: addresses valid, ALE high, no command. CS switch tristate wait states
• b phase: addresses valid, ALE high, no command. ALE length
• c phase: addresses valid, ALE low, no command. R/W delay
• d phase: write data valid, ALE low, no command. Data valid for write cycles
• e phase: command (read or write) active. Access time
• f phase: command inactive, address hold. Read data tristate time, write data hold
time
User Manual
a b c d
1-2 0-1
0-3 0-3
2
2 1 1
a b c d
0-3
1-2
0-3 0-1
2 1
2 1
6-155
User Manual
External Bus Controller
e
f
valid
valid
1-32 0-3
5 2rd
2wr
e f
valid
valid
1-32 0-3
5 2rd
2wr
V 1.7, 2001-01
C166S V2