Infineon Technologies C166S V2 User Manual page 429

Table 9-6 Register Overview Interrupt and PEC: Ordered by Address (cont'd)
Name Physical
Address
PECSEG5 EC8A
PECSEG6 EC8C
PECSEG7 EC8E
1)
EOPIC b F180
PECC0 FEC0
PECC1 FEC2
PECC2 FEC4
PECC3 FEC6
PECC4 FEC8
PECC5 FECA
PECC6 FECC
PECC7 FECE
1)
IRQxIC xxxx
PECISNC b FFA8
1)
The implementation and assignment of theses Interrupt Control Registers are product specific.
User Manual
8-bit
Address
--
H
--
H
--
H
E-C0
H H
60
H H
61
H H
62
H H
63
H H
64
H H
65
H H
66
H H
67
H H
xx
H H
D0
H H
Summary of CPU/Subsystem Registers
Description
PEC Pointer 5 Segment Address Reg. 0000
PEC Pointer 6 Segment Address Reg. 0000
PEC Pointer 7 Segment Address Reg. 0000
End of PEC Interrupt Control Reg.
PEC Channel 0 Control Register
PEC Channel 1 Control Register
PEC Channel 2 Control Register
PEC Channel 3 Control Register
PEC Channel 4 Control Register
PEC Channel 5 Control Register
PEC Channel 6 Control Register
PEC Channel 7 Control Register
Interrupt x Control Register
PEC Interrupt Subnode Control Reg.
9-429
User Manual
C166S V2
Reset
Value
H
H
H
0000
H
0000
H
0000
H
0000
H
0000
H
0000
H
0000
H
0000
H
0000
H
0000
H
0000
H
V 1.7, 2001-01