Infineon Technologies C166S V2 User Manual page 39

The respective halves of the byte-accessible registers have special names (see
Table 2-4). .
Table 2-4 Addressing modes to access Byte-GPRs
Name Physical
Address
1)
RL0 (CP)+0
RH0 (CP)+1
RL1 (CP)+2
RH1 (CP)+3
RL2 (CP)+4
RH2 (CP)+5
RL3 (CP)+6
RH3 (CP)+7
RL4 (CP)+8
RH4 (CP)+9
RL5 (CP)+10 FA
RH5 (CP)+11 FB
RL6 (CP)+12 FC
RH6 (CP)+13 FD
RL7 (CP)+14 FE
RH7 (CP)+15 FF
1)
Addressing mode only usable if the GPR bank is memory mapped.
Note: Even if the local register bank is selected by BANK, an old memory-mapped GPR
bank can be cached in the global register bank. Memory accesses are still
redirected in case of a cache hit.
User Manual
8-Bit 4-Bit
Address Address
F0 0h
H
F1 1h
H
F2 2h
H
F3 3h
H
F4 4h
H
F5 5h
H
F6 6h
H
F7 7h
H
F8 8h
H
F9 9h
H
Ah
H
Bh
H
Ch
H
Dh
H
Eh
H
Fh
H
Description
General Purpose Byte Register RL0
General Purpose Byte Register RL1
General Purpose Byte Register RL2
General Purpose Byte Register RL3
General Purpose Byte Register RL4
General Purpose Byte Register RL5
General Purpose Byte Register RL6
General Purpose Byte Register RL7
General Purpose Byte Register RL8
General Purpose Byte Register RL9
General Purpose Byte Register RL10 UU
General Purpose Byte Register RL11 UU
General Purpose Byte Register RL12 UU
General Purpose Byte Register RL13 UU
General Purpose Byte Register RL14 UU
General Purpose Byte Register RL15 UU
2-39
User Manual
C166S V2
Central Processing Unit
Reset
Value
UU
UU
UU
UU
UU
UU
UU
UU
UU
UU
V 1.7, 2001-01
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H