Infineon Technologies C166S V2 User Manual page 253

EXTPR
Begin EXTended Page and Register Sequence
Group
Syntax
Source Operand(s)
Destination Operand(s)
Operation
(count) ← (op2) [1 ≤ op2 ≤ 4]
Disable interrupts and Class A traps
Data_Page ← (op1)
SFR_range ← Extended
DO WHILE ((count) ≠ 0 AND Class_B_Trap_Condition ≠ TRUE)
END WHILE
(count) ← 0
Data_Page ← (DPPx)
SFR_range ← Standard
Enable interrupts and traps
Description
Overrides the standard DPP addressing scheme of the long and indirect addressing
modes and causes all SFR or SFR bit accesses via the 'reg', 'bitoff' or 'bitaddr'
addressing modes being made to the Extended SFR space for a specified number of
instructions. During their execution, both standard and PEC interrupts and class A
hardware traps are locked. For any long ('mem') or indirect ([...]) address in the EXTP
instruction sequence, the 10-bit page number (address bits A23-A14) is not determined
by the contents of a DPP register, but by the value of op1 itself. The 14-bit page offset
(address bits A13-A0) is derived from the long or indirect address as usual. The value
of op2 defines the length of the affected instruction sequence.
CPU Flags
E Not affected.
Z Not affected.
V Not affected.
User Manual
System Control Instructions
EXTPR op1, op2
op1 → 10-bit page number
op2 → 2-bit instruction counter
none
Next Instruction
(count) ← (count) - 1
E Z
- -
Detailed Instruction Description
V C
- -
8-253
User Manual
C166S V2
EXTPR
N
-
V 1.7, 2001-01