Infineon Technologies C166S V2 User Manual page 256

EXTS
Group
Syntax
Source Operand(s)
Destination Operand(s)
Operation
(count) ← (op2) [1
Disable interrupts and Class A traps
Data_Segment ← (op1)
DO WHILE ((count) ≠ 0 AND Class_B_Trap_Condition ≠ TRUE)
END WHILE
(count) ← 0
Data_Page ← (DPPx)
Enable interrupts and traps
Description
Overrides the standard DPP addressing scheme of the long and indirect addressing
modes for a specified number of instructions. During their execution, both standard and
PEC interrupts and class A hardware traps are locked. The EXTS instruction becomes
immediately active such that no additional NOPs are required. For any long ('mem') or
indirect ([...]) address in an EXTS instruction sequence, the value of op1 determines the
8-bit segment (address bits A23-A16) valid for the corresponding data access. The long
or indirect address itself represents the 16-bit segment offset (address bits A15-A0).
The value of op2 defines the length of the affected instruction sequence.
CPU Flags
E Not affected.
Z Not affected.
V Not affected.
C Not affected.
N Not affected.
User Manual
Begin EXTended Segment Sequence
System Control Instructions
EXTS op1, op2
op1 → segment number
op2 → 2-bit instruction counter
none
≤ ≤
op2
Next Instruction
(count) ← (count) - 1
E Z
- -
Detailed Instruction Description
4]
V C
- -
8-256
User Manual
C166S V2
EXTS
N
-
V 1.7, 2001-01