Infineon Technologies C166S V2 User Manual page 142

Field
CxIR
CxIE
1)
x = 7...0
2)
NOTE:
The "End of PEC" sub-node interrupt request flags are not cleared by hardware when entering the interrupt
service routine (interrupt has been accepted by the CPU), unlike the interrupt request flags of the interrupt
nodes (request flags xxIC.xxIR). The interrupt service routine must check the request flags and clear them
before executing the RETI instruction.
3)
It is recommended to clear an interrupt request flag (CxIR) before setting the respective enable flag (CxIE).
Otherwise, former requests still pending will immediately trigger an interrupt request after setting the enable bit.
User Manual
Bits Type Description
15, 13, rwh Interrupt Sub Node Request Flag of PEC
11, 9, Channel x
7, 5, 3, 0
1
1
14, 12, rw Interrupt Sub Node Enable Control Bit
10, 8, of PEC Channel x
6, 4, 2, (individually enables/disables a specific source)
0 0
1
Interrupt and Exception Handling
1) 2)
No special end of PEC interrupt request is
pending for PEC channel x
PEC channel x has raised an end of PEC
interrupt request
1) 3)
End of PEC interrupt request of PEC
channel x is disabled
End of PEC interrupt request of PEC
channel x is enabled
5-142
User Manual
C166S V2
V 1.7, 2001-01