Infineon Technologies C166S V2 User Manual page 136

not used to indicate hardware failures. After a Class A event, a dedicated service routine
is called to react to the events. Each Class A trap has its own vector location in the vector
table. After finishing the service routine, the instruction flow must be further correctly
executed. This explains why Class A traps cannot interrupt atomic/extend sequences
and I/O accesses in progress. For example, an interrupted extend sequence cannot be
restarted.
All Class A traps are generated in the pipeline during the execution of instructions, with
an exception of NMI, which is an asynchronous external event. It is not possible for two
different instructions in the pipeline to generate traps in the same CPU cycle. Class A
trap events can be generated only during the memory stage of execution. The execution
of instructions which caused a Class A trap event is always completed. In the case of a
Class A trap, the pipeline is directly canceled and the IP of the instruction following the
last executed one is pushed into the stack. In the case of an atomic/extend sequence or
I/O read access in progress, the execution continues till the sequence completion. Upon
completion of the sequence, the IP of the instruction following the last one executed is
pushed into the stack. Therefore, in the case of a Class A trap, the stack always contains
the IP of the first not-executed instruction in the instruction flow.
Note: The Branch Folding Unit allows an execution of branch instructions in parallel with
the preceding instruction. The pre-processed branch instruction is combined with
the preceding instruction. The branch is executed together with the instruction
which caused the Class A trap. The IP of the first following not-executed
instruction in the instruction flow is then pushed on the stack.
If more than one Class A trap occurs at a same time, they are prioritized internally. The
NMI trap has the highest priority and the software break has the lowest.
Note: In the case of two different Class A traps occurring simultaneously, both trap flags
are set. The IP of the instruction following the last one executed is pushed into the
stack. The trap with the higher priority is executed. After return from the service
routine, the IP is popped from the stack and immediately pushed again because
of the other pending Class A trap (unless the trap related to the second trap flag
in TFR has been cleared by the first trap service routine).
Class B Trap
Class B traps are generated by unrecoverable hardware failures. In the case of a
hardware failure, the CPU must immediately start a failure service routine. Class B traps
can interrupt an atomic/extend sequence and an I/O read access. After finishing the
Class B service routine, a restoration of the interrupted instruction flow is not possible.
All Class B traps have the same priority (trap priority I). When several Class B traps
become active at the same time, the corresponding flags in the TFR register are set and
the trap service routine is entered. Because all Class B traps have the same vector, the
priority of service of simultaneously occurring Class B traps is determined by the
software in the trap service routine.
User Manual
Interrupt and Exception Handling
5-136
User Manual
C166S V2
V 1.7, 2001-01