Infineon Technologies C166S V2 User Manual page 320

CoASHR
Accumulator Arithmetic Shift Right with Round
Group
Syntax
Source Operand(s)
Destination Operand(s)
Operation
(count) ← (op1)
(C) ← 0
DO WHILE (count) ≠ 0
END WHILE
(ACC) ← (ACC) + 0000 8000h
(MAL) ← 0
Description
Arithmetically shifts the ACC register right by the number of times as specified by the
operand op1. Then, the result is 2s complement rounded before being stored in the
40-bit ACC register. To preserve the sign of the ACC register, the most significant bits
of the result are filled with sign 0 if the original most significant bit was a 0 or with sign 1
if the original most significant bit was 1. Only shift values from 0 to 16 (inclusive) are
allowed. op1 can be either a 5-bit unsigned immediate data (the shift range is from 0 to
16 in this case) or the four least significant bits (the shift range is from 0 to 15 in that
case) of any register directly or indirectly addressed operand.
MAC Flags
MV MSL
* *
MV Set if an arithmetic overflow occurred. Cleared otherwise.
MSL Set if the contents of ACC is automatically saturated. Not affected
otherwise.
ME Set if the MAE is used. Cleared otherwise.
MSV Set if an arithmetic overflow occurred. Not affected otherwise.
MC Set if a carry is generated when rounding. Cleared otherwise.
MZ Set if result equals zero. Cleared otherwise.
MN Set if the most significant bit of the result is set. Cleared otherwise.
User Manual
Shift Instructions
CoASHR op1, rnd
op1 → shift counter
ACC → 40-bit signed value
(ACC[n]) ← (ACC[n+1]) [n=0...38]
(count) ← (count) -1
ME MSV
* *
Detailed Instruction Description
MC MZ
* *
8-320
User Manual
C166S V2
CoASHR
MN Sat.
* yes
V 1.7, 2001-01