Infineon Technologies C166S V2 User Manual page 128

PSW
Processor Status Word
15 14 13 12
ILVL
rwh
Field
ILVL
IEN
BANK
CPU Priority ILVL defines the current level for the CPU operation, thus, this bit field
reflects the priority level of the currently executed routine. When the CPU enters an
interrupt service routine this bit field is set to the priority level of the request that is being
serviced. The previous PSW is saved in the system stack before entering interrupt
service routine. To be serviced, any interrupt request must have a higher priority level
than the current CPU priority level. Any request of the same or a lower level will not be
acknowledged.
The current CPU priority level may be adjusted via software to select interrupt request
sources that can be serviced.
PEC transfers do not really interrupt the CPU, but rather "steal" some CPU cycle, so PEC
services do not influence the ILVL field in the PSW.
Hardware traps set the CPU level to the maximum priority (15). Therefore, no interrupt
or PEC requests will be acknowledged while an exception trap service routine is being
executed.
The TRAP instruction does not change the CPU level, so software trap service routines
may be interrupted by higher requests.
Register Bank BANK defines the currently used register bank for the CPU operation.
When the CPU enters an interrupt service routine, this bit field is updated to select the
register bank associated with the serviced request.
User Manual
bSFR
11 10 9 8
HLD
IEN BANK
EN
rw rw rwh
Bits Type Description
[15:12] rwh CPU Priority Level
0
H
...
F
H
[11] rw Interrupt/PEC Enable Bit (globally)
0
1
[9:8] rwh Reserved for register file bank selection
00
01
10
11
Interrupt and Exception Handling
7 6 5
MUL
USR1 USR0
IP
rwh r
rwh
Lowest Priority
...
Highest Priority
Interrupt/PEC requests are disabled
Interrupt/PEC requests are enabled
Global register bank
Reserved
Local register bank 1
Local register bank 2
5-128
User Manual
C166S V2
Reset Value: 0000
4 3 2 1
E Z V C
rwh rwh rwh rwh
V 1.7, 2001-01
H
0
N
rwh