Infineon Technologies C166S V2 User Manual page 255

EXTR
Group
Syntax
Source Operand(s)
Destination Operand(s)
Operation
(count) ← (op1) [1 ≤ op1 ≤ 4]
Disable interrupts and Class A traps
SFR_range ← Extended
DO WHILE ((count) ≠ 0 AND Class_B_Trap_Condition ≠ TRUE)
END WHILE
(count) ← 0
SFR_range ← Standard
Enable interrupts and traps
Description
Causes all SFR or SFR bit accesses via the 'reg', 'bitoff' or 'bitaddr' addressing modes
being made to the Extended SFR space for a specified number of instructions. During
their execution, both standard and PEC interrupts and class A hardware traps are
locked. The value of op1 defines the length of the affected instruction sequence.
CPU Flags
E Not affected.
Z Not affected.
V Not affected.
C Not affected.
N Not affected.
Encoding
Mnemonic
EXTR #irang2
User Manual
Begin EXTended Register Sequence
System Control Instructions
EXTR op1
op1 → 2-bit instruction counter
none
Next Instruction
(count) ← (count) - 1
E Z
- -
Detailed Instruction Description
V C
- -
Format
D1 :10##-0
8-255
User Manual
C166S V2
EXTR
N
-
Bytes
2
V 1.7, 2001-01