Infineon Technologies C166S V2 User Manual page 115

– For all the other instructions that modify this kind of CSFR, a simple stall and cancel
mechanism guarantees the correct instruction flow.
A possible explicit write-operation to this kind of CSFRs is detected on the Memory
stage of the pipeline. The following instructions on the Address and Decode Stage
are stalled. If the instruction reaches the execute stage, the entire pipeline and the
Instruction FIFO of the IFU are canceled. The instruction flow is completely re-
started.
I ........
n-1
I MOV PSW,R4
n
I MOV R6,R1
n+1
I ADD R6,R1
n+2
I MOV R3,[R0]
n+3
I ........
n+4
T
n+1
DECODE I =
n+1
MOV R6,R1
ADDRESS I =
n
MOV PSW,R4
MEMORY I
n-1
EXECUTE I
n-2
WRITE BACK I
n-3
User Manual
T T
n+2 n+3
I = I =
n+2 n+2
ADD R6,R1 ADD R6,R1
I = I =
n+1 n+1
MOV R6,R1 MOV R6,R1
I =
n
MOV PSW,R4
I I =
n-1 n
MOV PSW,R4
I I
n-2 n-1
4-115
Instruction Pipeline
T T
n+4 n+5
I =
n
MOV PSW,R4
User Manual
C166S V2
T
n+6
I =
n+1
MOV R6,R1
V 1.7, 2001-01