Infineon Technologies C166S V2 User Manual page 422

The first 8 GPRs (R7...R0) may be also accessed bytewise. Unlike SFRs, writing to a
GPR byte does not affect another byte of the GPR.
The following byte-accessible registers have special names.
Table 9-2 Addressing Modes to Access Byte–GPRs
Name Physical
Address
1)
RL0 (CP)+0
RH0 (CP)+1
RL1 (CP)+2
RH1 (CP)+3
RL2 (CP)+4
RH2 (CP)+5
RL3 (CP)+6
RH3 (CP)+7
RL4 (CP)+8
RH4 (CP)+9
RL5 (CP)+10 FA
RH5 (CP)+11 FB
RL6 (CP)+12 FC
RH6 (CP)+13 FD
RL7 (CP)+14 FE
RH7 (CP)+15 FF
1)
Addressing mode only usable if the GPR bank is memory mapped.
The 8-bit short addresses F0
access to the current register bank via short register addressing modes. The
GPRs are mirrored to the ESFR area which allows access to the current register
bank even after switching register spaces (see example below).
MOV R5, DP3
EXTR #1
MOV R5, ODP3 ;GPR access via ESFR area
User Manual
8-Bit 4-Bit
Address Address
F0 0h
H
F1 1h
H
F2 2h
H
F3 3h
H
F4 4h
H
F5 5h
H
F6 6h
H
F7 7h
H
F8 8h
H
F9 9h
H
Ah
H
Bh
H
Ch
H
Dh
H
Eh
H
Fh
H
...FE
H H
;GPR access via SFR area
Summary of CPU/Subsystem Registers
Description
General Purpose Byte Register RL0
General Purpose Byte Register RL1
General Purpose Byte Register RL2
General Purpose Byte Register RL3
General Purpose Byte Register RL4
General Purpose Byte Register RL5
General Purpose Byte Register RL6
General Purpose Byte Register RL7
General Purpose Byte Register RL8
General Purpose Byte Register RL9
General Purpose Byte Register RL10 UU
General Purpose Byte Register RL11 UU
General Purpose Byte Register RL12 UU
General Purpose Byte Register RL13 UU
General Purpose Byte Register RL14 UU
General Purpose Byte Register RL15 UU
within the ESFR area are reserved and provide
9-422
User Manual
C166S V2
Reset
Value
UU
H
UU
H
UU
H
UU
H
UU
H
UU
H
UU
H
UU
H
UU
H
UU
H
H
H
H
H
H
H
V 1.7, 2001-01