Infineon Technologies C166S V2 User Manual page 61

Table 2-8 DSP Addressing Modes (cont'd)
Mnemonic Particularities
with parallel In case of a CoXXXM instruction, the address stored in the specified
data move indirect address pointer is automatically pre-incremented by 2 for the
parallel move operation. The pointer itself is not pre-incremented. Then,
the specified indirect address pointer is automatically post-decremented
by 2 after the access.
[IDXx+QXx] The specified indirect address pointer is automatically post-incremented
by QXx after the access.
with parallel In case of a CoXXXM instruction, the address stored in the specified
data move indirect address pointer is automatically pre-decremented by QXx for
the parallel move operation. The pointer itself is not pre-decremented.
Then, the specified indirect address pointer is automatically post-
incremented by QXx after the access.
[IDXx-QXx] The specified indirect address pointer is automatically post-
decremented by QXx after the access.
with parallel In case of a CoXXXM instruction, the address stored in the specified
data move indirect address pointer is automatically pre-incremented by QXx for the
parallel move operation. The pointer itself is not pre-incremented. Then,
the specified indirect address pointer is automatically post-decremented
by QXx after the access.
The example in Figure 2-19
parallel move operation based on the descriptions about addressing modes given in
Section 2.5.2.4 (Indirect Addressing Modes) and
Modes).
User Manual
shows the complex operation of CoXXX instructions with a
2-61
Central Processing Unit
Section 2.5.3 (DSP Addressing
User Manual
C166S V2
V 1.7, 2001-01