Infineon Technologies C166S V2 User Manual page 37

For some instructions, only the first four GPRs can be used as indirect address pointers.
These GPRs are specified via short 2-bit GPR addresses. The respective physical
address calculation is identical with the one for the short 4-bit GPR addresses.
Short 8-Bit Register Addresses (mnemonic: reg or bitoff) within a range from F0
FF interpret the four least significant bits as short 4-bit GPR addresses, while the four
H
most significant bits are ignored. The respective physical GPR address is calculated
similar to the short 4-bit GPR addresses. For single bit GPR accesses, the GPR's word
address is calculated in the same way. The accessed bit position within the word is
specified by a separate additional 4-bit value.
12-Bit Context Pointer
11
Figure 2-10 Implicit CP Use by logical Short GPR Addressing Modes
.
24-Bit Memory Addresses can be directly used to access GPRs. In this case, the CPU
immediately starts the memory access. At the same time, a hit detection logic checks if
the accessed memory location is cached in the global register bank. In case of a cache
hit, an additional global register bank read access is initiated. The data that is read from
cache will be used and the data that is read from memory will be discarded. This leads
to a delay of one CPU cycle (MOV R4,mem [CP<=mem<=CP+31]). In case of memory
write access, the hit detection logic determines a cache hit in advance. Nevertheless, the
address conversion needs one additional CPU cycle. The value is directly written into the
global register bank without further delay (MOV mem,R4).
Note: The 24-bit GPR addressing mode is not recommended because it requires an
extra cycle for the read and write access.
User Manual
Specified by reg or bitoff
1 0
1 1 1 1 4-Bit GPR
address
For byte GPR
accesses *1
+
2-37
Central Processing Unit
For word GPR
*2
accesses
Must be within
the internal
DPRAM area
User Manual
C166S V2
to
H
Internal
DPRAM
GPRs
V 1.7, 2001-01