Infineon Technologies C166S V2 User Manual page 425

Table 9-4 Addressing Modes to Access Core-SFRs: Ordered by Address
Name Physical
Address
CSP FE08
MDH FE0C
MDL FE0E
CP FE10
SP FE12
STKOV FE14
STKUN FE16
CPUCON1 FE18
CPUCON2 FE1A
MAL FE5C
MAH FE5E
IDX0 b FF08
IDX1 b FF0A
SPSEG b FF0C
MDC b FF0E
PSW b FF10
VECSEG b FF12
ZEROS b FF1C
ONES b FF1E
TFR b FFAC
MRW b FFDA
MCW b FFDC
MSW b FFDE
1)
'??': defined by reset configuration
2)
'????': defined by reset configuration
User Manual
8-Bit Description
Address
04 Code Segment Pointer
H H
(8 bits, not directly writable)
06 Multiply Divide Register – High Word
H H
07 Multiply Divide Register – Low Word
H H
08 Context Pointer
H H
09 Stack Pointer
H H
0A Stack Overflow Register
H H
0B Stack Underflow Register
H H
0C Core Control Register
H H
0D Core Control Register
H H
2E MAC Accumulator – Low Word
H H
2F MAC Accumulator – High Word
H H
84 MAC Address Pointer 0
H H
85 MAC Address Pointer 1
H H
86 Stack Pointer Segment Register
H H
87 Multiply Divide Control Register
H H
88 Program Status Word
H H
89 Vector Table Segment Register
H H
8E Constant Value 0s Register (read only)
H H
8F Constant Value 1s Register (read only)
H H
D6 Trap Flag Register
H H
ED MAC Repeat Word
H H
EE MAC Control Word
H H
EF MAC Status Word
H H
Summary of CPU/Subsystem Registers
9-425
User Manual
C166S V2
Reset
Value
0000
H
0000
H
0000
H
FC00
H
FC00
H
FA00
H
FC00
H
0000
H
0000
H
0000
H
0000
H
0000
H
0000
H
0000
H
0000
H
0000
H
2)
????
H
0000
H
FFFF
H
0000
H
0000
H
0000
H
0200
H
V 1.7, 2001-01