Infineon Technologies C166S V2 User Manual page 58

Memory
255
254
x
1
0
Figure 2-18 CoMOV Operations and Addressing via the IDX Pointers
There are indirect addressing modes which allow parallel data move operations before
the long 16-bit address is calculated. Other indirect addressing modes allow
decrementing or incrementing the indirect address pointers (IDXx contents) by 2 or by
the contents of the offset registers. There are two non-bit addressable offset registers
QX0 and QX1 which can be used in conjunction with the CoXXX instructions.
User Manual
FF'0000
H
FE'0000
H
01'0000
H
00'0000
H
9 0
DPP
DPP3 - 11
DPP2 - 10
DPP1 - 01
DPP0 - 00
23 15 14
Page
Segment
2-58
User Manual
Central Processing Unit
16-Bit Data Address (IDXx)
15 14
selects DPP
Page offset
Segment offset
V 1.7, 2001-01
C166S V2
0
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