Infineon Technologies C166S V2 User Manual page 73

multiplication, this register represents the low order sixteen bits of the 32-bit result. For
long divisions, the MDL register must be loaded with the low order sixteen bits of the
32-bit dividend before the division has started. After any division, the MDL register
represents the 16-bit quotient.
MDL
Multiply Divide Low Word
15 14 13 12
Field
MDL
Whenever this register is updated via software, the Multiply/Divide Register In Use
(MDRIU) flag in the Multiply/Divide Control register (MDC) is set to 1. The MDRIU flag is
cleared whenever the MDL register is read via software.
The Divide Control Register MDC
This bit addressable 16-bit register is implicitly used by the CPU when it performs a
division or multiplication in the ALU.
MDC
Multiply Divide Control
15 14 13 12
0 0 0
r r r
Field
MDRIU
User Manual
11 10 9
Bits Type Description
[15:0] rwh
11 10 9
0 0 0 0
r r r r
Bits Type Description
[4] rwh Multiply/Divide Register In Use
0:
1:
SFR
8 7 6
MDL
rwh
Low part of MD
The low order 16 bits of the 32-bit multiply and
divide register MD.
SFRb
8 7 6
0 0 0
r r r
Cleared when MDL is read via software.
Set when MDL or MDH is written via
software, or when a multiply or divide
instruction is executed.
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User Manual
Central Processing Unit
Reset Value: 0000
5 4 3 2
Reset Value: 0000
5 4 3 2
MDR
0 0 0
IU
r rwh r r
V 1.7, 2001-01
C166S V2
H
1 0
H
1 0
0 0
r r